Clock signals within integrated circuits are utilized to control the movement of data and synchronize control signals. Typically, a specified amount of time after the estimated receipt of the leading edge of a clock signal, data transfer is accomplished within the integrated circuit. Many prior art methods for clock distribution are plagued by distortions or delays on the rising edge of the clock signal. If the rising edge is too late, the data transfer does not occur as required.
Large designs require many different circuits to be synchronized and operate at the same speed. In such systems, a high frequency clock signal must be distributed over a large chip area. Currently, attempts to distribute clock signals in the range of one gigahertz are faltering due to the parasitic properties of long wires and long wire terminations. As the attenuation of the transmission line circuit and wiring load increases, the clock signal power level at transmission line terminations (circuit clock inputs) decreases. Transmission line circuit loading and interconnect wiring attenuation can be very high in present systems. A sub-circuit receiving a weak clock signal can cause serious design difficulties.
The propagation delay of a signal, due to long wires and multiple sinks, can be reduced by “repowering” or relaying the signal utilizing simple amplifiers, called buffers. FIG. 1 illustrates a current solution in buffering clock signals in digital communications systems. The approach is to buffer a single clock signal from a clock source 10 referenced to a common ground and a common power supply with a “single-ended” buffer circuit 12a for a load circuit 14a. As more circuits 14b . . . 14n are added to a given clock source, more “single-ended” buffer circuits 12b . . . 12n are added in series to buffer the clocking signal from the source 10 to the destination circuit 14. Unfortunately, more noise is added to the clocking signal as each additional circuit is added to the clock signal path. Further, buffers introduce uncertainties in the timing of integrated circuits and require chip area.
Accordingly, a need exists for an integrated circuit clock distribution system that has high noise immunity and readily accommodates additional circuits in a clock signal path. The present invention addresses such a need.